High speed integrated circuits formed on a crystalline semiconductor wafer have ultra shallow semiconductor junctions formed by ion implanting dopant impurities into source and drain regions. The implanted dopant impurities are activated by a high temperature anneal step which causes a large proportion of the implanted atoms to become substitutional in the crystalline semiconductor lattice. Such a post-ion implantation anneal step is performed using a dynamic laser surface anneal process in which a thin line of intense radiation is scanned in a direction transverse to the line across the wafer surface. The scanning rate of the line beam is sufficiently great so that heating of the wafer (to a temperature between 1150 to 1350 degrees C.) is limited to an extremely shallow depth below the surface and to an extremely narrow region corresponding to the thin laser line beam. The narrow region temporarily expands.
The dynamic surface anneal process employs an array of diode lasers whose multiple parallel beams are focused along a narrow line (e.g., about 300 microns wide) having a length less than the wafer diameter or radius. The diode lasers have a wavelength of about 810 nm. The narrow laser beam line is scanned transversely across the wafer surface (e.g., at a rate between 30 mm/sec to 300 mm/sec), so that each point on the wafer surface is exposed for a very short time (e.g., between 0.25 millisec to 5 millisecs). This type of annealing is disclosed in United States Patent Publication No. US 2003/0196996A1 (Oct. 23, 2003) by Dean C. Jennings et al. Each region of the wafer surface reaches a temperature range of about 1150-1300 degrees C. for about 50 microsec to 3 millisec. The depth of this region is about 10-20 microns. This depth is sufficient because it extends well-below the ultra-shallow semiconductor junction depth of about 200 Angstroms. Such a high temperature is sufficient to activate the implanted (dopant) atoms and to anneal lattice damage or defects. Some of these defects like end of range defects may require laser exposure time of 1 mellisec to 3 millisec above 1150-1350 degrees C., to fully or to partially resolve end of range defects to a level where their presence does not impact device performance. The optical absorption of the laser radiation must be uniform across the wafer surface for uniform dopant activation.
The problem is that the underlying thin film structures formed on the wafer surface present different optical absorption characteristics and different optical emissivities in different locations on the wafer surface. This makes it difficult if not impossible to attain uniform anneal temperatures across the wafer surface. This problem can be solved by depositing an optical absorption layer over the entire wafer surface that uniformly absorbs the laser radiation and then conducts the heat to the underlying semiconductor wafer. Such a film must withstand the stress of heating during the laser anneal step without damage or separation, and must be selectively removable after the laser anneal step with respect to underlayers and must not contaminate or damage the underlying semiconductor wafer or thin film features. The problem of withstanding stress arises from the thermal expansion of the narrow laser-illuminated portion of the wafer surface. Further, the absorber film must attain excellent step coverage (high degree of conformality) over the underlying thin film features.
An amorphous carbon material is the best choice for the optical absorber layer, as suggested in U.S. Patent Publication No. 2005/0074986, filed Jan. 15, 2004 by Luc Van Autryve et al. entitled “Absorber Layer for DSA Processing” and assigned to the present assignee, which discloses a plasma enhanced chemical vapor deposition (PECVD) process for depositing the amorphous carbon layer. One advantage of amorphous carbon is that it is readily removed with high selectivity by oxidation at a low wafer temperature. Another advantage is that carbon is generally compatible with semiconductor plasma processes and therefore does not involve contamination, so long as excessive implantation does not occur.
One problem is that the deposited layer is vulnerable to cracking or peeling under the high temperatures of the laser anneal step, unless the layer is deposited at a very high temperature (e.g., 550 degrees C.). Unfortunately, such a high temperature causes clustering of the implanted dopant atoms during the deposition step itself. Such clustered dopant atoms resist separation during the subsequent laser anneal step, limiting the fraction of the implanted atoms that move during the laser anneal step into substitutional sites in the crystal. This results in unacceptably high sheet resistance in the source or drain regions.
These issues are not problems in the fabrication of semiconductor structures with larger (e.g., 65 nm) feature sizes. This is because the larger gate-source overlap (20 nm) permitted for such larger structures can be annealed by conventional thermal (flash lamp) annealing (prior to deposition of the optical absorber layer). This anneal step is then followed by the dynamic surface (laser) anneal step to obtain a fractional improvement in dopant activation. This improvement is limited because the thermal annealing causes a small amount of dopant clustering which the subsequent laser annealing step cannot undo. The 45 nm devices require better dopant activation, which requires elimination of the thermal annealing step and maintaining wafer temperatures below the threshold (475 degrees C.) at which dopant clustering can occur until the laser anneal step is performed. This results in extremely high dopant activation levels and low sheet resistance in the implanted areas, as required for 45 nm device structures. The requirement to maintain the wafer temperature below the dopant clustering threshold temperature is critical in the 45 nm process (unlike the 65 nm process) because none of the implanted dopant atoms have been moved into substitutional crystal sites prior to laser annealing (since the thermal annealing step is not permitted), so that any elevation of the wafer temperature prior to laser annealing (e.g., during the amorphous carbon layer deposition) threatens to cluster all of the dopant atoms, which would make it impossible to obtain sufficient dopant activation even by laser annealing.
Attempting to avoid this problem by reducing the wafer temperature (e.g., below 475 degrees C.) during PECVD deposition of the absorber layer creates two problems. First, the mechanical properties of the deposited amorphous carbon layer formed at this lower temperature are inferior so that it will fail (by cracking, peeling or separation from the wafer) during the laser annealing step. Secondly, the amorphous carbon layer deposited at the lower temperature has inferior or insufficient optical absorption qualities (low extinction coefficient) at the 810 nm wavelength of the laser anneal step. The lower extinction coefficient requires a thicker optical absorber (amorphous carbon) layer to attain 90-99% absorption of the laser power. The increased thickness increases the susceptibility of the absorber layer to peel or separate during the dynamic laser anneal step. The extinction coefficient may be so low that the amorphous carbon layer is transparent to the 810 nm laser light regardless of thickness, and therefore is not functional.
What is needed is a low temperature (i.e., less than 475 degrees C.) deposition process which provides an amorphous carbon layer having a high optical extinction coefficient at the wavelength of the laser anneal step (i.e., an extinction coefficient greater than 0.35 at a wavelength of 81 nm) and which is impervious to mechanical failure such as peeling or separation at the temperature of the laser annealing step (e.g., 1150 to 1350 degrees C.), and which has excellent step coverage. Such a process has not seemed possible.